tagRegisterFile Project Status
Project File: project1.xise Parser Errors: X 1 Error
Module Name: tagRegisterFile Implementation State: Synthesized
Target Device: xc3s500e-5fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
3 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 4 4656 0%
Number of Slice Flip Flops 8 9312 0%
Number of 4 input LUTs 8 9312 0%
Number of bonded IOBs 21 232 9%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Oct 16 14:05:36 201703 Warnings (1 new)3 Infos (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed Oct 11 20:37:42 2017
WebTalk ReportOut of DateWed Oct 11 20:15:24 2017
WebTalk Log FileOut of DateWed Oct 11 20:15:26 2017

Date Generated: 10/18/2017 - 11:57:56