tagRegisterFile Project Status | |||
Project File: | project1.xise | Parser Errors: | X 1 Error |
Module Name: | tagRegisterFile | Implementation State: | Synthesized |
Target Device: | xc3s500e-5fg320 |
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No Errors |
Product Version: | ISE 14.7 |
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3 Warnings (1 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 4 | 4656 | 0% | |
Number of Slice Flip Flops | 8 | 9312 | 0% | |
Number of 4 input LUTs | 8 | 9312 | 0% | |
Number of bonded IOBs | 21 | 232 | 9% | |
Number of GCLKs | 1 | 24 | 4% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mon Oct 16 14:05:36 2017 | 0 | 3 Warnings (1 new) | 3 Infos (0 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Wed Oct 11 20:37:42 2017 | |
WebTalk Report | Out of Date | Wed Oct 11 20:15:24 2017 | |
WebTalk Log File | Out of Date | Wed Oct 11 20:15:26 2017 |