Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
main_processor|Datapath_Circuit|operationSel |
130 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|regZero |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|regCarry |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|notber |
32 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|negMux |
65 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|lsl1 |
32 |
1 |
1 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|lsr1 |
32 |
1 |
1 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|or1 |
64 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|and1 |
64 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p32 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p31 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p30 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p29 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p28 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p27 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p26 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p25 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p24 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p23 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p22 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p21 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p20 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p19 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p18 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p17 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p16 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p15 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p14 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p13 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p12 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p11 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p10 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p9 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p8 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p7 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p6 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p5 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p4 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p3 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p2 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1|p1 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|adder1 |
65 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit|mux1 |
259 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|alu_Unit |
67 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|operand2 |
130 |
32 |
0 |
32 |
32 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|operand1 |
65 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|dataMem |
43 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|mux_Data |
65 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|reducer |
32 |
0 |
24 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|regB |
35 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|regA |
35 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|muxB |
65 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|muxA |
65 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|pc_compo |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|lze1 |
32 |
16 |
16 |
16 |
32 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|uze1 |
32 |
16 |
16 |
16 |
32 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit|ir |
35 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor|Datapath_Circuit |
60 |
72 |
0 |
72 |
266 |
72 |
72 |
72 |
0 |
0 |
0 |
0 |
0 |
main_processor|Control_Circuit |
37 |
1 |
24 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
main_processor|Reset_Circuit1 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_processor |
35 |
27 |
0 |
27 |
200 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
main_memory|altsyncram_component|auto_generated |
40 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
main_memory |
40 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |